In electronic design automation, an integrated circuit (IC) floorplan schematically represents tentative placement of the major functional blocks associated with the IC. In modern electronic design processes, floorplans are typically created during the floorplanning stage, which is an early stage in the hierarchical approach to chip design. Floorplanning takes into account some of the geometrical constraints in a design, including, for example, the location of bonding pads for off-chip connections. Furthermore, in electronic design, an intellectual property (IP) block (or IP core) refers to a reusable logic unit, cell, or chip layout design that is considered the intellectual property of a particular party. As such, IP blocks may be used as building blocks within IC designs by parties that have licensed and/or own the intellectual property that exists in the design (e.g., patents, source code copyrights, trade secrets, know-how, etc.). In general, there may be various advantages to using three-dimensional (3D) IP blocks in combination with 2D IP blocks to improve the overall quality of full-chip 3D IC designs.
For example, a 3D semiconductor device (or stacked IC device) can contain two or more semiconductor devices that are stacked vertically and thereby occupy less space than two or more conventionally arranged semiconductor devices. The stacked IC device is a single integrated circuit built by stacking silicon wafers and/or ICs that are interconnected vertically so as to behave as a single device. Conventionally, the stacked semiconductor devices are wired together using input/output (I/O) ports at the perimeter of the device and/or across the area of the device. The I/O ports slightly increase the length and width of the assembly. In some new 3D stacks, a technique referred to as Through Silicon Stacking (TSS) uses through-silicon-vias (TSVs) to completely or partly replace edge wiring by creating vertical connections through the body of the semiconductor device such that stacked IC devices can pack substantial functionality into a small footprint. However, device scaling and interconnect performance mismatch has increased exponentially and is expected to continue to increase even further. This exponential increase in device and interconnect performance mismatch has forced designers to use techniques such as heavy buffering of global interconnects, which increases chip area and power consumption.
As such, current 3D methodologies that focus on assembling 2D blocks into 3D stacks only help to reduce the inter-block nets, if applicable, without leveraging the 3D IC within the blocks and leaving further improvements on the table. On the other hand, starting from an existing 2D IP block, a technique called “block folding” can perform tier partitioning and redo placement and routing for all tiers under the same footprint in order to create 3D IP blocks and thereby build the final 3D IP layout. However, existing techniques that utilize block folding do not address how to place I/O pins in the folded 3D IP blocks, which may have a major impact on the final 3D IC design quality in terms of wirelength, area, and the number of TSVs used for inter-block connections.